STM32之定時(shí)器應(yīng)用

定時(shí)控制的寄存器包括； TIMX_CR1;TIMX_CR2;TIMX_SMCR;TIMX_DIERTIMX_SR;TIMX_EGR;TIMX_CCMR1;TIMX_CCMR2;TIMX_CCER;TIMX_CNT;TIMX_PSC;TIMX_ARR;TIMX_RCR;TIMX_CCR1;TIMX_CCR2;TIMX_CCR3;TIMX_CCR4;TIMX_BDTR;TIMX_DCR;TIMX_tDMAR;各個(gè)寄存器配置：

void TIMER_X_Init(TIM_TypeDef* TIMx,uint16_t TIM_ClockDivision,uint16_t TIM_Prescaler)

{

if(TIMx==TIM1)

RCC->APB2ENR =1<<11;

if(TIMx==TIM2)

RCC->APB1ENR|=1<<0;

if(TIMx==TIM3)

RCC->APB1ENR|=1<<1; //時(shí)鐘使能

if(TIMx==TIM4)

RCC->APB1ENR|=1<<2;

TIMx->ARR=TIM_Prescaler; //設(shè)定計(jì)數(shù)器自動(dòng)重裝值

TIMx->PSC=TIM_ClockDivision; //預(yù)分頻器

//TIMx->CR1 |=~(1<<4); //計(jì)數(shù)方向1上0下

TIMx->DIER|=1<<0; //允許更新中斷

TIMx->DIER|=1<<6; //允許觸發(fā)中斷

TIMx->CR1 |=0x01; //使能定時(shí)器

}

用庫(kù)函數(shù)：

void TIM2_Init(void) //TIM2初始化函數(shù)

{

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;

RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2,ENABLE); //定時(shí)器2外設(shè)時(shí)鐘使能

TIM_DeInit(TIM2); //復(fù)位定時(shí)器2

TIM_TimeBaseStructure.TIM_Period=TIM2_T; //定時(shí)器初始值

TIM_TimeBaseStructure.TIM_Prescaler=71; //時(shí)鐘預(yù)分頻

TIM_TimeBaseStructure.TIM_ClockDivision=TIM_CKD_DIV1; //時(shí)鐘分割

TIM_TimeBaseStructure.TIM_CounterMode=TIM_CounterMode_Up; //向上計(jì)數(shù)模式

TIM_TimeBaseInit(TIM2,&TIM_TimeBaseStructure); //初始化定時(shí)器的值

TIM_ClearFlag(TIM2,TIM_FLAG_Update); //清除定時(shí)器中斷標(biāo)志

TIM_ITConfig(TIM2,TIM_IT_Update,ENABLE); //使能中斷

TIM_Cmd(TIM2,ENABLE); //開(kāi)啟時(shí)鐘

TIM_SetAutoreload(TIM2, TIM2_T); //設(shè)置定時(shí)器2重裝載值

TIM_ARRPreloadConfig(TIM2, ENABLE); //定時(shí)器2自動(dòng)重裝使能

}

pwm寄存器模式：

void TIMERX_PWM_Init(TIM_TypeDef* TIMx,uint16_t PSC,uint16_t ARR,uint8_t CH)

{ RCC->APB2ENR|=0X0001;

if(TIMx==TIM1) RCC->APB2ENR =1<<11;

if(TIMx==TIM2) RCC->APB1ENR|=1<<0;

if(TIMx==TIM3) RCC->APB1ENR|=1<<1; //時(shí)鐘使能

if(TIMx==TIM4) RCC->APB1ENR|=1<<2; TIMx->ARR=ARR; //設(shè)定計(jì)數(shù)器自動(dòng)重裝值

TIMx->PSC=PSC; //預(yù)分頻器

switch(CH) {

case 1:TIMx->CCR1=ARR/2;TIMx->CCMR1 |=7<<4; TIMx->CCMR1 |=1<<3;TIMx->CCER|=1<<0; break;

case 2:TIMx->CCR2=ARR/2;TIMx->CCMR1 |=7<<12; TIMx->CCMR1 |=1<<11;TIMx->CCER|=1<<4; break;

case 3:TIMx->CCR3=ARR/2;TIMx->CCMR2 |=7<<4; TIMx->CCMR1 |=1<<3;TIMx->CCER|=1<<8; break;

case 4:TIMx->CCR4=ARR/2;TIMx->CCMR2 |=7<<12; TIMx->CCMR1 |=1<<11;TIMx->CCER|=1<<12; break;

} TIMx->CR1=0x0080; //ARPE使能 TIMx->CR1 |=0x01; //使能定時(shí)器

}

pwm庫(kù)函數(shù)：

void PWM_Init(void)

{

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;

TIM_OCInitTypeDef TIM_OCInitStructure;

/* TIM1, GPIOA, GPIOB, GPIOE and AFIO clocks enable */

RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 |RCC_APB2Periph_AFIO, ENABLE);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 ;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOA, &GPIO_InitStructure);

/* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */

TimerPeriod = (SystemCoreClock / PWM_Frequency ) - 1;

/* Compute CCR1 value to generate a duty cycle at 50% for channel 1 and 1N */

Channel1Pulse = (uint16_t) (((uint32_t) PWM_Duty * (TimerPeriod - 1)) / 1000);

/* Time Base configuration */

TIM_TimeBaseStructure.TIM_Prescaler = 0;

TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;

TIM_TimeBaseStructure.TIM_Period = TimerPeriod;

TIM_TimeBaseStructure.TIM_ClockDivision = 0;

TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;

TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);

/* Channel 1, 2,3 and 4 Configuration in PWM mode */

TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;

TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;

TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;

TIM_OCInitStructure.TIM_Pulse = Channel1Pulse;

TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;

TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;

TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;

TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;

TIM_OC1Init(TIM1, &TIM_OCInitStructure);

/* TIM1 counter enable */

TIM_Cmd(TIM1, ENABLE);

/* TIM1 Main Output Enable */

TIM_CtrlPWMOutputs(TIM1, ENABLE);

}