基于網(wǎng)絡(luò)編碼的多信源組播通信系統(tǒng)，包括源代碼，原理圖等(四)
英飛凌汽車電子生態(tài)圈
else begin
本文引用地址：http://m.butianyuan.cn/article/201612/326827.htmdata_router_multiplier_1 <= data_temp1;
val_router_multiplier_1 <= 1;
if (ctrl_temp1 == 8'hff) begin
first_dword_1 <= 1;
rand_num_en <= 1;
end
else begin
first_dword_1 <=0;
rand_num_en <= 0;
end
router_status <= SEND_BOTH_2;
end
end //state SEND_BOTH_1 ends
SEND_BOTH_2: begin
first_dword_1 <= 0;
val_router_multiplier_1 <= 0; //clear valid signal
//confirm the first random number is generated successfully
//before enable to generate the second.
if (ctrl_temp1 == 8'hff) begin
if (!rand_num_val) begin
rand_num_en <= 0;
router_status <= SEND_BOTH_2;
end
end else begin
if (!rdy_router_multiplier_2) begin
val_router_multiplier_2 <= 0;
router_status <= SEND_BOTH_2;
end
else begin
data_router_multiplier_2 <= data_temp2;
val_router_multiplier_2 <= 1;
if (ctrl_temp2 == 8'hff) begin
first_dword_2 <= 1;
rand_num_en <= 1;
end
else begin
first_dword_2 <= 0;
rand_num_en <= 0;
end
if (((ctrl_temp1 == 8'hf0) && (& (ctrl_temp2))) || ((ctrl_temp2 == 8'hf0) && (& (ctrl_temp1)))) begin
router_status <= JUDGE;
end
else begin
rd_en_payloadfifo_router_1 <= 1;
rd_en_payloadfifo_router_2 <= 1;
counter_getdata <= 0;
router_status <= GET_BOTH;
end
end
end
end //state SEND_BOTH_2 ends
endcase
end
end
endmodule
附2：解碼路由器核心代碼之一：解碼控制模塊：decode_control_sm. v
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// Copyright(c) 2009, All rights reserved.
// Advanced Network technology Lab, Shenzhen graduated school of PKU
// Module: decode_control_sm.v
// Project: NF2.1
// Time and Author: 2009-12-15 zhang ming long
// Description: According to the pkts' source and generation sequence number,
// this module goes round-robin strategy to control the module decoder
// to decode the pkts stored in DRAMS.
///////////////////////////////////////////////////////////////////////////////
`define DLY #1
`timescale 1ns/1ps
module decode_control_sm
#(parameter SRC_WIDTH = 4,
parameter GEN_WIDTH = 8,
parameter REG_GRP_WIDTH = 12,
parameter SRC_GEN_SEQ_WIDTH = 24,
parameter DRAM_NUMS = 3,
parameter CAM_NUMS = 3,
parameter DRAM_NUMS_WIDTH = log2(DRAM_NUMS),
parameter CAM_NUMS_WIDTH = log2(CAM_NUMS),
parameter DRAM_BLOCK_WIDTH = 8,
parameter CAM_ADDR_WIDTH = 8,
parameter CMP_DATA_MASK = 12'hfff
)
(// --- cam interface
output [SRC_GEN_SEQ_WIDTH-1:0] cmp_data_0,
output reg [SRC_GEN_SEQ_WIDTH-1:0] cmp_data_mask_0,
input [CAM_ADDR_WIDTH-1:0] match_addr_0,
input match_0,
output [SRC_GEN_SEQ_WIDTH-1:0]
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