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EEPW首頁(yè) > 模擬技術(shù) > 設(shè)計(jì)應(yīng)用 > Linear LTC2259-16 16位模-數(shù)轉(zhuǎn)換方案

Linear LTC2259-16 16位模-數(shù)轉(zhuǎn)換方案

作者: 時(shí)間:2010-04-22 來(lái)源: 收藏
Linear 公司的是 16位器,適用于對(duì)高頻寬動(dòng)態(tài)范圍的信號(hào)進(jìn)行數(shù)字化.它的SNR為73.1dB,SFDR為88dB,單電源1.8V工作,功率89mW,具有CMOS, DDR CMOS 或DDR LVDS輸出,可選擇的輸入范圍從1VP-P 到 2VP-P,主要用于,,SDR,,多路數(shù)據(jù)采集和非破壞性測(cè)試.本文介紹了LTCR2259-16主要特性, 功能方框圖, 采用變壓器模擬輸入(5MHz-70MHz)電路圖,以及70MHz到170MHz, 170MHz到270MHz, 大于270MHz和采用高速差分放大器的前端輸入電路圖, 典型應(yīng)用電路圖.

The LTCR2259-16 is a sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 73.1dB SNR and 88dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±4LSB INL (typical) and ±0.5LSB DNL (typical).

The digital outputs can be either full-rate CMOS, doubledata rate CMOS, or double-data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

LTCR2259-16主要特性:

73.1dB SNR

88dB SFDR

Low Power: 89mW

Single 1.8V Supply

CMOS, DDR CMOS or DDR LVDS Outputs

Selectable Input Ranges: 1VP-P to 2VP-P

800MHz Full-Power Bandwidth S/H

Optional Data Output Randomizer

Optional Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

Serial SPI Port for Configuration

40-Pin (6mm x 6mm) QFN Package

LTCR2259-16應(yīng)用:

Communications

Cellular Base Stations

Software Defi ned Radios

Portable Medical Imaging

Multi-Channel Data Acquisition

Nondestructive Testing


圖1.LTCR2259-16功能方框圖

圖2.LTCR2259-16采用變壓器模擬輸入(5MHz-70MHz)電路圖

圖3.LTCR2259-16 70MHz到170MHz前端輸入電路圖

圖3.LTCR2259-16 170MHz到270MHz前端輸入電路圖

圖4.LTCR2259-16 大于270MHz前端輸入電路圖

圖5.LTCR2259-16 采用高速差分放大器的前端輸入電路圖

圖6. 應(yīng)用電路


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