如何降低能耗的可編程邏輯器件的設(shè)計(jì)，電源供應(yīng)自行車

將復(fù)雜可編程邏輯器件（CPLDs）應(yīng)用于需要嚴(yán)格功率預(yù)算的系統(tǒng)變得越來越普遍。例如：智能手機(jī)、手持儀表、錄像設(shè)備和導(dǎo)航裝置。盡管一些“零功耗”CPLDs待機(jī)時(shí)的功耗可以微安計(jì)算，但這些裝置滿足不了一些特殊設(shè)計(jì)的要求。在這種情況下，電動(dòng)自行車設(shè)計(jì)人員必須提供一個(gè)可行的方案去實(shí)現(xiàn)低功耗。

負(fù)載循環(huán)中功耗減少是有事實(shí)根據(jù)的，這個(gè)事實(shí)就是大多數(shù)現(xiàn)在的設(shè)備通常很少用CPLD處理需求。例如：CPLD可以掃描鍵盤，看看關(guān)鍵通訊是否已經(jīng)發(fā)生，或者等待串行接口上的一些連接信號(hào)。
CPLDs向所有的集成電路一樣，不管運(yùn)行與否都會(huì)由于設(shè)備的傾向和泄漏從而產(chǎn)生功耗。而且裝置內(nèi)信號(hào)的開關(guān)CPLDs也會(huì)產(chǎn)生功耗。這個(gè)功耗叫做動(dòng)態(tài)功耗。
動(dòng)態(tài)功耗與實(shí)現(xiàn)的處理程序數(shù)量是成正比的。因此，0.1秒、100MHz時(shí)實(shí)現(xiàn)操作的功耗與在10秒、1MHz實(shí)現(xiàn)操作所需功耗幾乎是一樣的。

通過在短的時(shí)間范圍內(nèi)避免活動(dòng)的要求和在休止的時(shí)候關(guān)掉CPLD的方式，動(dòng)態(tài)和靜態(tài)功耗的這些特點(diǎn)可以把設(shè)計(jì)的功耗降到最低。

1.1負(fù)載循環(huán)方法概述

For the duty cycle approach to work, the power up and down time of the CPLD clearly needs to be brief compared with the frequency at which the CPLD must be activated in order to achieve the desired processing and system response time.為占空比工作方式，功率和時(shí)間的CPLD實(shí)現(xiàn)顯然需要很簡(jiǎn)短的頻率相比，在這次會(huì)議上CPLD的必須啟動(dòng)，以達(dá)到理想的加工和系統(tǒng)響應(yīng)時(shí)間。 Fortunately, currently available CPLD devices utilize on-chip, non-volatile memory that yields power up and down times below 1 mS.幸運(yùn)的是，現(xiàn)有的基于CPLD器件利用片上非易失性存儲(chǔ)器的產(chǎn)量權(quán)力向上和向下次低于1毫秒。 This allows CPLDs to be activated at frequencies up to the low hundreds of Hz while still yielding useful power savings due to the duty cycling approach.這使得CPLDs被激活頻率達(dá)低幾百赫茲同時(shí)還產(chǎn)生有益的省電由于工作地點(diǎn)騎自行車的方式。

Implementing the switch 執(zhí)行開關(guān)
When implementing the duty cycle approach, it is necessary to engineer the design so that it is possible to turn the CPLD device on and off.當(dāng)執(zhí)行工作周期的辦法，有必要的設(shè)計(jì)工程師，以便有可能把CPLD的裝置和關(guān)閉。 There are several methods available to achieve this.有幾種方法可實(shí)現(xiàn)這一目標(biāo)。 However, the method chosen will be influenced by several factors.然而，選擇的方法將受到幾個(gè)因素的影響。 Key factors to consider include:關(guān)鍵要考慮的因素包括：


The number of power supplies the CPLD has.人數(shù)的CPLD的電力供應(yīng)已。
What other devices, if any, share power supplies with the device.還有哪些其他設(shè)備，如果有的話，共享電源裝置。
Whether devices sharing the same power supply rail can be duty cycled.無論是設(shè)備共享相同的電力供應(yīng)鐵路可免稅循環(huán)。
The controls available within the power supply subsystem for disabling power supplies在控制范圍內(nèi)現(xiàn)有的電源子系統(tǒng)禁用電源
There are three primary methods that can be considered when implementing duty cycling of the CPLD.有三個(gè)主要方法，可以被視為執(zhí)行職責(zé)時(shí)，騎自行車的CPLD實(shí)現(xiàn)。 The advantages and disadvantages of each method are described below.的優(yōu)點(diǎn)和缺點(diǎn)每個(gè)方法介紹如下。

Use Power Supply Disable on the Voltage Regulator Module (VRM) : Many designs use VRMs to provide power to the chips within the design, and often these modules have a power enable/disable input signal that can be used to duty cycle the CPLD. 電源使用禁用的電壓調(diào)節(jié)器模塊（ VRM ） ：許多設(shè)計(jì)使用VRMs提供電力的芯片的設(shè)計(jì)，而且往往是這些模塊的電源啟用/禁用輸入信號(hào)，可用于占空比的可編程邏輯器件。 The advantage of this approach is its relative simplicity.這種方法的優(yōu)點(diǎn)是其相對(duì)簡(jiǎn)單。 One disadvantage of this approach is its course grained nature, requiring all devices that are fed by the particular module to be cycled on and off at the same time.一個(gè)缺點(diǎn)是它的這種做法當(dāng)然晶性質(zhì)，要求所有設(shè)備，特別是美聯(lián)儲(chǔ)的模塊循環(huán)和關(guān)閉在同一時(shí)間。 The second disadvantage is that the time required to power down and power up the VRM reduces the frequency at which the duty cycling can occur.第二個(gè)缺點(diǎn)是，所需要的時(shí)間自動(dòng)關(guān)閉電源和功率降低了VRM的頻率稅騎自行車，就可能發(fā)生。

Use FETs on the Power Lines to the CPLD(s) : In this approach FETs (Field Effect Transistors) are placed in the various power supply lines of the CPLD to be duty cycled. 使用場(chǎng)效應(yīng)管的電力線路上的可編程邏輯器件（補(bǔ)） ：在這個(gè)辦法場(chǎng)效應(yīng)管（場(chǎng)效應(yīng)晶體管）被安置在各供電線路的CPLD實(shí)現(xiàn)的義務(wù)循環(huán)。 This approach has two key advantages.這種做法有兩個(gè)關(guān)鍵優(yōu)勢(shì)。 First, it allows specific device(s) to be duty cycled.首先，它可以讓特定裝置（縣）的工作地點(diǎn)循環(huán)。 Second, the power can be turned on and off very rapidly, which allows the device to be duty cycled at a higher frequency.第二，權(quán)力可以開啟和關(guān)閉非常迅速，這使得該器件成為義務(wù)循環(huán)在更高的頻率。 The disadvantage of this approach is that additional devices are required on the circuit board, driving up cost and board area.這種辦法的缺點(diǎn)是，需要額外的設(shè)備上的電路板，推高的成本和電路板面積。

Use CPLD Sleep-Pin Functionality : An increasing number of PLDs, such as Lattice's MachXO family, incorporate a sleep pin that allows the device to be disabled and the static power consumption reduced to almost zero. 使用CPLD的睡眠引腳功能 ：越來越多的可編程邏輯器件，如Lattice的MachXO家庭，納入了“睡眠引腳”使設(shè)備被禁用和靜態(tài)功耗降低到幾乎為零。 This functionality can be used to implement duty cycling.這項(xiàng)功能可以用來執(zhí)行責(zé)任騎自行車。 With this approach, only the specific CPLD is duty cycled and the turn on and off times allow for a high frequency of duty cycling.用這個(gè)辦法，只有具體的CPLD的是騎自行車和義務(wù)打開和關(guān)閉時(shí)間允許高頻工作地點(diǎn)騎自行車。 This approach also uses minimal components, saving cost and board area.這種方法還利用最少的元件，節(jié)省成本和電路板面積。

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