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EEPW首頁 > 模擬技術(shù) > 設(shè)計(jì)應(yīng)用 > 監(jiān)測集成電路監(jiān)控電池供電設(shè)備

監(jiān)測集成電路監(jiān)控電池供電設(shè)備

作者： 時(shí)間：2012-01-30 來源：網(wǎng)絡(luò) 收藏
I/O line high for about 30μs, then configures the line as a high-impedance input. The comparator in IC1 drives BATT OK high, which pulls BATT high and latches it in that condition. The comparator is powered by VCC, so its output in the high state is near VCC. If VCC goes as low as 2.25V at any time during the sleep period, the comparator output snaps low and pulls BATT low, latching it in the low condition. After VCC is restored (by recharging the main battery or replacing it) the μC polls BATT before proceeding: high indicates a warm boot, and low indicates a cold boot.

μCs such as the Motorola 68HC11 have bidirectional reset pins that may contend with active-low RESET from the supervisory IC. If the supervisor reset is high, for instance, and the μC tries to pull it low, the result may be an indeterminate logic level. Figure 8 connections allow both the supervisor and μC to assert valid resets to the system, and also ensure sufficient duration for the reset pulses (μC resets may be too short for some devices in the system).

監(jiān)測集成電路監(jiān)控電池供電設(shè)備
Figure 8. These connections allow dual control of the buffered reset line, and extend the duration of resets issued by the μP.

The capacitor enables resets from the supervisor and μC to pull active-low MR low. active-low MR going low initiates a 200ms timeout within the supervisor, producing a 200ms minimum pulse at its active-low RESET terminal (pin 2) that overrides the μC active-low RESET and drives the system reset line via the buffer. active-low MR returns high as the capacitor charges. When the μC active-low RESET de-asserts following the timeout delay, the capacitor discharges through the active-low MR pull-up resistor and an internal ESD-protection diode.
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