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基于FPGA的PS/2鼠標(biāo)接口設(shè)計(jì)方法及其應(yīng)用

作者: 時(shí)間:2012-02-08 來源:網(wǎng)絡(luò) 收藏

when m2_hold_clk_l =>
ps2_clk_hi_z = '0'; -- 啟動(dòng)看門狗!
if (watchdog_timer_done='1') then
m2_next_state = m2_data_low_1;
else
m2_next_state = m2_hold_clk_l;
end if;
when m2_data_low_1 =>
ps2_data_hi_z = '0'; -- 數(shù)據(jù)位 開始位, d[0] and d[1]
if (fall='1' and (bitcount = 2)) then
m2_next_state = m2_data_high_1;
else
m2_next_state = m2_data_low_1;
end if;
when m2_data_high_1 =>
ps2_data_hi_z = '1'; -- 數(shù)據(jù)位 d[2]
if (fall='1' and (bitcount = 3)) then
m2_next_state = m2_data_low_2;
else
m2_next_state = m2_data_high_1;
end if;
when m2_data_low_2 =>
ps2_data_hi_z = '0'; -- 數(shù)據(jù)位 d[3]
if (fall='1' and (bitcount = 4)) then
m2_next_state = m2_data_high_2;
else
m2_next_state = m2_data_low_2;
end if;
when m2_data_high_2 =>
ps2_data_hi_z = '1'; -- 數(shù)據(jù)位 d[4],d[5],d[6],d[7]
if (fall='1' and (bitcount = 8)) then
m2_next_state = m2_data_low_3;
else
m2_next_state = m2_data_high_2;
end if;
when m2_data_low_3 =>
ps2_data_hi_z = '0'; -- 奇偶校驗(yàn)位
if (fall='1') then
m2_next_state = m2_data_high_3;
else
m2_next_state = m2_data_low_3;
end if;
when m2_data_high_3 =>
ps2_data_hi_z = '1'; -- 允許鼠標(biāo)拉成低電平(ACK脈沖)
if (fall='1' and (ps2_data='1')) then
m2_next_state = m2_error_no_ack;
elsif (fall='1' and (ps2_data='0')) then
m2_next_state = m2_await_response;
else
m2_next_state = m2_data_high_3;
end if;
when m2_error_no_ack =>
error_no_ack = '1';
m2_next_state = m2_error_no_ack;

-- 為了鼠標(biāo)正確進(jìn)入"streaming"模式,狀態(tài)極必須等待足夠長(zhǎng)的時(shí)間,確保鼠標(biāo)正確應(yīng)答0xFA。

when m2_await_response =>
--if (bitcount = 22) then
m2_next_state = m2_verify;
--else
-- m2_next_state = m2_await_response;
--end if;
when others => m2_next_state = m2_wait;
end case;
end process;-----------------------------m2 狀態(tài)結(jié)束
-- 位計(jì)數(shù)器 (略)
-- 數(shù)據(jù)移位寄存器(略)
-- 看門狗時(shí)間計(jì)數(shù)器(略)
watchdog_timer_done = '1' when (watchdog_timer_count=WATCHDOG-1) else '0';
packet_good = '1'; -- 接收數(shù)據(jù)包有效標(biāo)志
outdata: process (reset, clk) -- 輸出數(shù)據(jù)
begin
if (reset='0') then
left_button = '0';
right_button = '0';
elsif (clk'event and clk='1') then
if (output_strobe='1') then
left_button = q(1);
right_button = q(2);
mouseyy = not (q(6) q(6) q(30 downto 23)) + "1";
end if;
end if;
end process;
cordinatex: process (reset, clk)
begin
if (reset='0') then
mousex = "0110010000"; -- 400
elsif (clk'event and clk='1') then
if (output_strobe='1') then
if ((mousex >= 797 and q(5)='0') or (mousex = 2 and
q(5)='1')) then
mousex = mousex;
else
mousex = mousex + (q(5) q(5) q(19 downto
12));--q(5):xsign q(6):ysign
end if;
end if;
end if;
end process;
cordinatey: process (reset, clk)
begin
if (reset='0') then
mousey = "0100101100"; -- 300
elsif (clk'event and clk='1') then
if (output_strobe='1') then
if ((mousey >= 597 and q(6)='1') or (mousey = 2
and q(6)='0')) then
mousey = mousey;
else
m ousey = mousey + mouseyy; --(q(6) q(6) q(30
downto 23));
end if;
end if;
end if;
end process;
data_ready = output_strobe;
end Behavioral;


結(jié)束語

  該設(shè)計(jì)采用了清華大學(xué)THCII-1創(chuàng)新SoPC實(shí)驗(yàn)套件進(jìn)行綜合、仿真和下載,測(cè)試得到了滿意的效果,完整地實(shí)現(xiàn)了對(duì)PS/2和VGA的時(shí)序驅(qū)動(dòng)。

  該設(shè)計(jì)可以被應(yīng)用到各種需要鼠標(biāo)操作、以VGA作為顯示的中,從而大大提高人機(jī)交互能力,降低了開發(fā)成本,提高了開發(fā)效率,使系統(tǒng)的穩(wěn)定性也得到了可靠的保障。


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