電路板EMC準則總結(jié)

1.1 Component Placement
Ø         Place components on the board before determining connector pin assignments.

Ø         Let the circuit board layout dictate the connector pin location and function assignment.

Ø         Divide the circuit board into different DC voltage areas (12 VDC area, 5 VDC area, etc.).

Ø         Laterally segregate components based on the DC voltage that they use.

Ø         Do not allow different DC voltage planes to overlap one another.

Ø         Components using multiple DC voltages must straddle the boundary between the different voltage areas.

Ø         Keep all connectors on the same edge of the board.

Ø         Keep MHz circuits away from connectors. Do not allow MHz circuits to be located between connectors.

Ø         Keep all I/O drivers very close to the connector. Avoid letting the I/O lines come too far onto the board.

Ø         Provide space for shunt capacitors on all I/O lines.

Ø         Locate components to minimize the length of high speed clock lines.

1.2 DC Power Distribution
Ø         Do not allow different DC voltage planes to overlap one another. For example the +5V and +15V planes should not overlap. Bipolar DC voltage planes, such as +15V and –15V, should overlap.

Ø         Maximize the distributed capacitance in the DC power bus. Ideally, use parallel power and return planes with a Z0 < 1Ω.

Ø         Minimize the series inductance of any lumped decoupling capacitors. For boards with power and return planes, this inductance is caused by the traces and vias that connect the capacitor to the planes.

Ø         Provide at least one decoupling capacitor (1-100nF) for each integrated circuit DC power pin. Provide bulk decoupling (μF) where the DC power comes onto the board and at the output of each voltage regulator and DC-DC convertor.

Ø         For boards with power and return planes, the integrated circuits share all the decoupling capacitors on the board.

1.3 Routing of Signal Output and Return Paths
Ø         Current takes the path of least impedance. Above 10kHz this usually means the smallest loop area path.

Ø         All critical signals (DC power, high frequency, large amplitude or small amplitude) need a closely located return path. Prefer signal and return traces < 0.1” apart.

Ø         Treat all critical signals as current loops. Check each critical loop area before the board is built.

Ø         The return (ground) plane may require gaps to control the path of kHz currents. Do not use gaps to control the flow of MHz currents.

Ø         No trace should be permitted to cross any gaps in the return plane.

Ø         A small loop area is more important than short trace lengths.

Ø         The spacing between any trace and the board edge should not be less than the spacing to the return plane.

1.4 Signal Integrity – Reducing Crosstalk and Distortion
Ø         Self shielding occurs when the return current is allowed to surround the outgoing current, as in a coaxial cable.

Ø         Traces on adjacent layers should be oriented perpendicular to one another.

Ø         Ringing may indicate excessive wiring inductance.

Ø         Rounding may indicate excessive capacitance.

Ø         Unintended sharp transitions in signal level may indicate reflections due to impedance mismatches.

Ø         Separate high current, low frequency (kHz) return paths (ground) from low current return paths. Connect the high and low current returns together at only one point.

Ø         Connect “guard traces” to the return plane on both ends so that the traces can serve as additional signal return paths.

Ø         Do not allow any electrically floating metal.

Ø         Connect all metal fill areas to the return plane.

Ø         Connect all unused integrated circuit gate inputs to either return (ground) or +VDC.

1.5 High Frequency Transmission Lines
Ø         A trace may need to be treated as a transmission line when trace length >

    λ/20, or propagation delay > (pulse rise time)/4.

Ø         Use a Z0 > 40Ω to minimize the drive current and a Z0 < 120Ω to reduce emission and susceptibility.

Ø         Unintended sharp transitions in signal level may indicate reflections due to impedance mismatches.

Ø         The time delay for the arrival of a reflection may indicate the distance to the impedance mismatch.

1.6 Reducing Conducted and Radiated Emissions
Ø         Keep all metal structures at the same RF voltage.

Ø         Do not use gaps in the return plane, except to control the location of low frequency (kHz) currents.

Ø         Do not allow any traces to cross any gaps in the return plane.

Ø         Most low frequency (kHz) I/O lines need HF(MHz) decoupling to the signal return (Ground) at the connector to reduce VDM applied to the cable.

Ø         The circuit board signal return needs a HF (MHz) connection to any surrounding metal chassis at the connector to reduce VCM applied to the cable.

Ø         Use the longest rise time possible for all pulse signals.

Ø         Use logic families that are no faster than necessary.

Ø         Use the lowest clock frequency possible.

Ø         Keep all clock lines as short as possible.

Ø         Tightly control the loop area of all high speed signals.

Ø         Do not split or gap the return plane under any connector.

Ø         For filter capacitors to be effective near 100MHz, essentially zero lead length is required. An “X” style lead connection may be necessary for a shunt capacitor.