基于FPGA的中文字符顯示的VHDL程序
--文件名:lcd_driver.vhd。
本文引用地址:http://m.butianyuan.cn/article/149005.htm--最后修改日期:2004.3.24。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_driver is
Port ( clk : in std_logic; --狀態(tài)機(jī)時鐘信號,同時也是液晶時鐘信號,其周期應(yīng)該滿足液晶數(shù)據(jù)的建立時間
reset:in std_logic;
lcdda : out std_logic; --寄存器選擇信號
lcdrw : out std_logic; --液晶讀寫信號
lcden : out std_logic; --液晶時鐘信號
data : out std_logic_vector(7 downto 0)); --液晶數(shù)據(jù)信號
end lcd_driver;
architecture Behavioral of lcd_driver is
type state is (set_dlnf,set_cursor,set_dcb,set _cgram,write _cgram,set_ddram,write_data);
signal current_state:state;
type ram2 is array(0 to 7) of std_logic_vector(7 downto 0);
constant cgram:ram2:=((00001000),(00001111),(00010010),
(00001111),(00001010),(00011111),(00000010),(00000010));--年字符數(shù)據(jù)存儲器
signal clkk : std_logic;
begin
lcden = clk ; --液晶時鐘信號
lcdrw = '0' ; --寫數(shù)據(jù)
control:process(clk,reset,current_state) --液晶驅(qū)動控制器
variable cnt1: std_logic_vector(2 downto 0);
begin
if reset='0'then
current_state=set_dlnf;
cnt1:=(others => '1');
lcdda='0';
elsif rising_edge(clk)then
current_state = current_state ;
lcdda = '0';
case current_state is
when set_dlnf=>
data=00111100;--3cH
current_state=set_cursor;
when set_cursor=>
data=00000110;--06H
current_state=set_dcb;
when set_dcb=>
data=00001111;--0fH
current_state=set_ cgram;
when set_ cgram=>
data=01000000;--40H
current_state=write_ cgram;
when write_ cgram=> --向CGRAM中寫入“年”
lcdda='1';
cnt1:=cnt1+1;
data=cgram(conv_integer(cnt1));
if cnt1 = 111 then
current_state=set_ddram;
end if;
when set_ddram=> --從第一行的起始地址開始顯示
data=10000000;--80H
current_state=write_data;
when write_data=>
lcdda='1';
data=00000000; --寫入字符“年”
when others => null;
end case;
end if;
end process;
end Behavioral;
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