VHDL設(shè)計中信號與變量問題的研究

　　library ieee;

　　use ieee.std_logic_1164.all;

　　use ieee.std_logic_unsigned.all;

　　entity sevenauto is

　　port(clk:in std_logic;

　　y:out std_logic_vector(6 downto 0));

　　end sevenauto;

　　architecture behave of sevenauto is

　　begin

　　process(clk)

　　variable count:std_logic_vector(3 downto 0);

　　variable init:std_logic;

　　begin

　　if (clk''event) and (clk=''1'') then

　　if (init = ''0'') then

　　count:= "1001";

　　init:=''1'

　　end if;

　　count:=count+1;

　　case count is

　　when "0000"=>y="1111110";

　　when "0001"=>y="0110000";

　　when X"2"=>y="1101101";

　　when X"3"=>y="1111001";

　　when X"4"=>y="0110011";

　　when X"5"=>y="1011011";

　　when X"6"=>y="1011111";

　　when X"7"=>y="1110000";

　　when X"8"=>y="1111111";

　　when X"9"=>y="1111011";

　　when X"A"=>y="1110111";

　　when X"B"=>y="0011111";

　　when X"C"=>y="1001110";

　　when "1101"=>y="0111101";

　　when "1110"=>y="1001111";

　　when "1111"=>y="1000111";

　　when thers=>y="XXXXXXX";

　　end case;

　　end if;

　　end process;

　　end behave;