Freescale MC56F8257數(shù)字信號(hào)控制器開發(fā)方案
Freescale公司的MC56F825x/MC56F824x是基于56800E核的數(shù)字信號(hào)控制器(DSC),集成了DSP的處理功能和MCU功能以及靈活的豐富外設(shè),便于創(chuàng)建高性價(jià)比的解決方案.60MHz時(shí)的性能為60MIPS,工作電壓3.0V-3.6V,工作溫度–40℃到+105 ℃,主要用于工業(yè)控制,家用電器,智能傳感器,消防和安全系統(tǒng),太陽(yáng)能逆變器,電池充電和管理,開關(guān)電源和管理,馬達(dá)控制,電表,手持電動(dòng)工具,醫(yī)療設(shè)備,儀表和照明鎮(zhèn)流器等.本文介紹了MC56F825x/MC56F824x主要特性,框圖和56800E核框圖, MC56F8257 Tower MCU模塊TWR-56F8257主要特性,方框圖,電路圖和材料清單.
本文引用地址:http://m.butianyuan.cn/article/148321.htmThe MC56F825x/MC56F824x is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create a cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, it is well-suited for many applications. The MC56F825x/MC56F824x includes many peripherals that are especially useful for cost-sensitive applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Solar inverters
• Battery chargers and management
• Switched-mode power supplies and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical devices/equipment
• Instrumentation
• Lighting ballast
The 56800E core is based on a modified Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.
The MC56F825x/MC56F824x supports program execution from internal memories. Two data operands per instruction cycle can be accessed from the on-chip data RAM. A full set of programmable peripherals supports various applications.
Each peripheral can be independently shut down to save power. Any pin, except Power pins and the Reset pin, can also be configured as General Purpose Input/Outputs (GPIOs).
On-chip features include:
• 60 MHz operation frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• On-chip memory
– 56F8245/46: 48 KB (24K x 16) flash memory; 6 KB (3K x 16) unified data/program RAM
56F8247: 48 KB (24K x 16) flash memory; 8 KB (4K x 16) unified data/program RAM
– 56F8255/56/57: 64 KB (32K x 16) flash memory; 8 KB (4K x 16) unified data/program RAM
• eFlexPWM with up to 9 channels, including 6 channels with high (520 ps) resolution NanoEdge placement
• Two 8-channel, 12-bit analog-to-digital converters (ADCs) with dynamic x2 and x4 programmable amplifier, conversion time as short as 600 ns, and input current-injection protection
• Three analog comparators with integrated 5-bit DAC references
• Cyclic Redundancy Check (CRC) Generator
• Two high-speed queued serial communication interface (QSCI) modules with LIN slave functionality
• Queued serial peripheral interface (QSPI) module
• Two SMBus-compatible inter-integrated circuit (I2C) ports
• Freescale’s scalable controller area network (MSCAN) 2.0 A/B module
• Two 16-bit quad timers (2 x 4 16-bit timers)
• Computer operating properly (COP) watchdog module
• On-chip relaxation oscillator: 8 MHz (400 kHz at standby mode)
• Crystal/resonator oscillator
• Integrated power-on reset (POR) and low-voltage interrupt (LVI) and brown-out reset module
• Inter-module crossbar connection
• Up to 54 GPIOs
• 44-pin LQFP, 48-pin LQFP, and 64-pin LQFP packages
• Single supply: 3.0 V to 3.6 V
MC56F825x/MC56F824x主要特性:
Core
• Efficient 56800E digital signal processor (DSP) engine with modified Harvard architecture
— Three internal address buses
— Four internal data buses
• As many as 60 million instructions per second (MIPS) at 60 MHz core frequency
• 155 basic instructions in conjunction with up to 20 address modes
• 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical operation
• Single-cycle 16 × 16-bit parallel multiplier-accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
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