選擇合適的系列電壓基準(zhǔn)源的絕對精度電壓輸出
加入技術(shù)交流群
Design D: Low Voltage, Battery Powered, Moderate Accuracy
No calibration or trimming is planned for Design D, so the A-grade MAX6190 initial error of 1600ppm (106 × 2mV/1.25V) is used directly in the error budget, along with 150ppm (30°C × 5ppm/°C) for the tempco error. The 75ppm temperature hysteresis is also used directly, but the risk of using this typical specification is at least partially offset by the reduced operating-temperature range (15°C to 45°C). Once again, the 1000-hour long-term stability is doubled to 100ppm as a conservative estimate of the drift, as there is no burn-in in this application.The load-regulation error is again calculated from the assumed worst-case MAX5176 DAC reference input current of 69μA:
| Load-Regulation Error | = 69μA × 0.5μV / μA = 34.5μV (max) |
| = 106 × 34.5μV / 1.25V = 28ppm (max) |
The power supply varies between 2.7V and 3.6V in this design, so the MAX6190 line-regulation specification of 80μV/V (max) must be included in the analysis:
| Line-Regulation Error | = (3.6V - 2.7V) × 80μV / V = 72μV (max) |
| = 106 × 72μV / 1.25V = 58ppm (max) |
As with Design C, the bandwidth for Design D is specified as 0.1Hz to 10Hz, so we use half of the 25μVp-p low-frequency (1/f) noise specification to arrive at a peak noise contribution of 10ppm at the reference output (106 × [12.5μV/1.25V]). We expect the same 10ppm-reference-induced noise term at the DAC output, because the reference voltage and noise see the same DAC gain.
Focusing now on the MAX5176 DAC error terms, the A-grade INL is ±2LSB, which is 488ppm on the 12-bit scale. The DAC worst-case gain error of +/-8LSB with a 5kΩ load translates to 1953ppm at 12 bits. Like the MAX5170 in Design B, the MAX5176 does not specify a gain-error tempco. This is not a concern in Design D, because it is not a low-drift design calibrated at one temperature and the maximum DAC gain error is specified over the entire operating-temperature range. The final consideration is the MAX5176's DAC output noise, whose estimated typical peak value is assumed to be negligible ([106 × (√10Hz × π/2) × 80nVRMS/√Hz × √2]/2.048V) ~ = 0.22ppm).
As with Designs B and C, the worst-case error of 4462ppm exceeds the 3906ppm target error, whereas the 2580ppm RSS error is well below the target. Based on these numbers, Design D is considered to be successful, because it comfortably meets the requirements from an RSS standpoint and has demonstrated the important design concepts. If further improvement is desired, alternative DACs should be considered first, because the MAX6190 is the best low-power voltage reference available with an output below 1.3V (caused by the VDD - 1.4V limitation on DAC reference inputs) and such low quiescent current (35μA).
DAC Voltage-Reference Design Summary
This article has demonstrated a design procedure for DAC voltage-reference selection involving the following steps:Step 1. Voltage Ranges and Reference-Voltage Determination: The power-supply voltage and the DAC output-voltage range were used to determine viable reference-voltage and DAC gain options.
Step 2. Initial Voltage-Reference Device-Selection Criteria: Candidate voltage references were considered, focusing on reference voltage (determined in Step 1), initial accuracy, tempco, and reference output current. From these candidates, an initial device was selected.
Step 3. Final Specification Review and Error-Budget Analysis: The selected voltage-reference and DAC candidates were evaluated using an error-budget approach to see if they met the design's overall accuracy requirements. To meet the design goals, iteration between Steps 2 and 3 may be required.
When following the design procedure described above, it's convenient to do the error analysis in ppm and to understand how it relates to other system-accuracy and error measures (Table 6).
Table 6. Accuracy and Error Ranges
相關(guān)推薦技術(shù)專區(qū)
|
評論